1. Field of the Invention
The present invention relates to a split transaction bus system, in particular, to a split transaction bus system having an improved read response speed.
2. Description of the Prior Art
In an information processing system in which a bus is shared among a plurality of devices, an arbiter is generally provided to arbitrate among the plurality of devices each requesting a bus ownership. In the case of a legacy bus, a device serving as a master transmits a bus request to the arbiter, receives a bus grant from the arbiter, and then start using the bus to conduct a write or read to or from a slave device. When the bus requests from two or more devices compete each other, a priority device is selected according to a preset priority logic, and the bus grant is transmitted thereto. A typical priority logic used is a scheme in which the priority is fixed or round robin scheduling in which the priority is changed for every arbitration. The master device having received the bus ownership transmits a read or a write command to a slave device via the bus, and then data is read from the slave device or written to the slave device. The master device occupies the bus during the period between the transmission of the command and the completion of the read or write. In the case of read, in particular, the bus is not released during a time required for data access in the slave device. In the case where a processor serving as the master device sends the read request to a memory serving as the slave device, the data is likely to be one immediately needed by the processor for processing, so that, in one aspect, it is advantageous to wait for the read response while occupying the bus. In another aspect, however, since another master device cannot use the bus if the slave device needs a long access time, a problem arises in that the utilization ratio of the bus is reduced.
For improving the utilization ratio of the bus, a split transaction bus is known. The split transaction bus allows the slave device to request the bus ownership from the arbiter. When the bus request from the master device is the request for read, the master device receives the bus grant from the arbiter, issues the read command to the bus, and then releases once the bus. The slave device, which has received the read command, transmits the bus request to the arbiter when the data is ready for output after a lapse of the access time.
FIG. 1A is, an operation timing chart for a conventional split transaction bus. Two master devices and two slave devices are connected to the split transaction bus, and the bus ownership is arbitrated by the arbiter. Assume that, at a time t1, a bus request REQ(M1) from a first master device and a bus request REQ(M2) from a second master device are simultaneously issued. The arbiter determines to give the bus grant to the first master device according to a priority logic. At a time t2, the first master device receives the bus grant GNT(M1). At a time t3, the first master device issues a read command RR for a first slave device to the bus. After issuing the read command RR, the first master device releases the bus ownership at a time t4. The arbiter transmits a bus grant GNT(M2) to the second master device, which continuously transmits the bus request REQ(M2) . At a time t5, the second master device issues a write command WR for the second slave device to the bus. The second master device starts transferring write data WD at a time t6, completes a write cycle at a time t8, and then releases the bus ownership.
After a lapse of 5 clock cycles, which is equivalent to the read access time for the read command RR from the first master device, the first slave device transmits a bus request REQ(S1) for the read response to the arbiter at a time t9. At a time t10, the arbiter transmits the bus grant GNT(S1) to the first slave device. At a time t11, the first slave device starts transferring the read data RD to the first master device via the bus.
As described above, since in the split transaction bus, the first master device having made the read request releases the bus after issuing the read command RR, the second master device can use the bus during the access time of the first slave device, and therefore, the utilization ratio of the bus is improved.
However, in the first conventional split transaction bus, read data acquisition by the master device may be significantly delayed when the bus request for the read response and the bus request for block write or burst write for write-transferring a plurality of pieces of data compete each other. This problem will be described with reference to the operation timing chart shown in FIG. 1B. The operation from the time t1 to t8 is the same as that shown in FIG. 1A. Assume that the second master device transmits the bus request REQ(M2) to the arbiter at a time t9, the bus request REQ(M2) competes with the bus request REQ(S1) for the read response from the first slave device, and the arbiter transmits the bus grant GNT(M2) to the second master device. In response to the bus grant, at a time t11, the second master device issues the write command WR to the second slave device, and then at a time t12, transfers the write data WD. Since the bus is occupied during the period from the time t11 to t13, the start of transfer of the read data RD from the first slave device is delayed to a time t14.
A second conventional arbitration method for the split transaction bus having solved this problem is described in Japanese Patent Laid-Open No. 8-263428. In this second conventional method, the arbiter gives the bus ownership in response to the bus request by priority unless the bus is being used. According to this method, the time between the transmission of the bus request from the slave device and the output of the read data RD to the bus can be reduced. In the case where the second conventional method is applied, as shown in an operation timing chart of FIG. 2, the arbiter issues the bus grant GNT(S1) to the slave device at the time t10, so that transfer of the read data RD is started as the time t11. At the time t13 after the transfer of the read data RD is completed, the bus grant GNT(M2) in response to the bus request REQ(M2) from the second master device is issued, and at a time t14, the second master device outputs the write command WR to the bus.
In this second conventional method also, however, when competition with the bus request from another master device occurs, the time period for transmitting the bus grant from the time t10 to t11, that is, an arbitration cycle is required, and thus there is yet room for improvement.
As a technique of reducing an overhead required for switching the bus grant, a system based on,a legacy bus system and having a parking function of previously transmitting the bus grant to a particular master device added thereto is known. As for the parking, a bus system capable of designating a default owner, to which the bus ownership is given by default when no master device uses the bus, that is, the bus is in a free state (idle state), is described in Japanese Patent Laid-Open No. 11-25035. In addition, in Japanese Patent Laid-Open No. 2000-35943, there is described a technique of analyzing a predetermined number of the last transactions for the master devices to determine one using the bus most frequently as the master device to be parked.
In the legacy bus system, however, only the master devices can transmit the bus request and acquire the bus grant. Even in the case of the system having the parking function, such as techniques described in Japanese Patent Laid-Open Nos. 11-25035 and 2000-35943, the target of the parking is limited to the master devices. Therefore, although it is possible to indirectly improve the read response by applying these techniques to advance the issue of the read command from the master device, it is impossible to directly improve the read response from the slave device. In addition, even if the well-known parking function is applied to the split transaction bus, since the only the master devices can be the target of the parking, the arbitration cycle is still required for the transaction for the read response, and the read response cannot be directly improved.
Although the split transaction bus may be configured to park the slave device, which is a target of the read, immediately after the read command is issued, in such a case, the master device cannot be parked after the read command is issued. Therefore, in the case where another bus request from another master device is received during the period between the issue of the read command and the transmission of the bus request from the slave device, which is the target of the read, the arbitration cycle for the arbiter is required to cancel the parking and issue the bus grant to the master device. In addition, once the bus ownership is passed to another master device, the parking of the slave device is cancelled. Thus, the arbitration cycle for the arbiter occurs also for a subsequent read response from the slave device, so that the parking of the slave device after the read command is issued goes for nothing.
The present invention is devised in view of such a circumstance, and an object of this invention is to provide a split transaction bus system having an improved parking function, an improved read response speed, and reduced occurrence of an arbitration cycle.
In order to attain the object, a split transaction bus system according to this invention comprises: a bus that is a data transfer path for a plurality of devices; two or more master devices connected to the bus and each having an output terminal for a bus request and an input terminal for a bus grant; one or more slave devices connected to the bus and each having an output terminal for a bus request and an input terminal for a bus grant; an access time prediction circuit that predicts an access time required for the data in the slave device to be read to be ready for output when a read command is issued from one of the master devices to one of the slave devices, measures an elapsed time based on a count of clock signals, and sends a parking indication to the slave device to be read during the last cycle before the predicted access time; and an arbiter having an input terminal for the bus request from the master device and the slave device and an output terminal for the bus grant to the master device and the slave device, and provided with an arbitration function of selecting the device to which a bus ownership is given in response to the bus request thereof and transmitting the bus grant thereto, and a parking control function of parking the slave device to be read by transmitting the bus grant to the slave device to be read unless the bus is being used when the parking indication is received, as well as placing the slave device to be read at the highest priority in the arbitration.
According to another aspect of this invention, the split transaction bus comprises: a bus that is a data transfer path for a plurality of devices; two or more master devices connected to the bus and each. having an output terminal for a bus request and an input terminal for a bus grant; one or more slave devices connected to the bus and each having an output terminal for a bus request and an input terminal for a bus grant; an access time prediction circuit that predicts an access time required for the data in the slave device to be read to be ready for output when a read command is issued from one of the master devices to one of the slave devices, measures an elapsed time based on a count of clock signals, and sends a parking indication to the slave device to be read during the last cycle before the predicted access time; and an arbiter having an input terminal for the bus request from the master device and the slave device and an output terminal for the bus grant to the master device and the slave device, and provided with an arbitration function of selecting the device to which a bus ownership is given in response to the bus request thereof and transmitting the bus grant thereto, and a parking control function of parking the slave device to be read by, if the bus is not being used when the parking indication is received, transmitting the bus grant to the slave device to be read, and if write is being executed, depriving the master device of the bus ownership and transmitting the bus grant to the slave device to be read, as well as placing the slave device to be read at the highest priority in the arbitration.
According to another aspect of this invention, the split transaction bus comprises: a bus that is a data transfer path for a plurality of devices; two or more master devices connected to the bus and each having an output terminal for a bus request and an input terminal for a bus grant; one or more slave devices connected to the bus and each having an output terminal for a bus request and an input terminal for a bus grant; an access time prediction circuit that predicts an access time required for the data in the slave device to be read to be ready for output when a read command is issued from one of the master devices to one of the slave devices, measures an elapsed time based on a count of clock signals, and sends a parking indication to the slave device to be read during the last cycle before the predicted access time; and an arbiter having an input terminal for the bus request from the master device and the slave device, an output terminal for the bus grant to the master device and the slave device and a connection terminal to the bus, and provided with an arbitration function of selecting the device to which a bus ownership is given in response to the bus request thereof and transmitting the bus grant thereto, and a parking control function of parking the slave device to be read by, if the bus is not being used when the parking indication is received, transmitting the bus grant to the slave device to be read, and if write is being executed, calculating, based on information of the read command and the write command received from the bus, the number of clock cycles required for completing a write process at the time when the predicted access time elapses and the number of clock cycles required for data read from the slave device to be read, and comparing the numbers with each other, and when the former number is equal to or more than the latter number, depriving the master device of the bus ownership and transmitting the bus grant to the slave device to be read, as well as placing the slave device to be read at the highest priority in the arbitration.
These and other objects and features of this invention will be apparent from the description with reference to the drawings and the new matters as set forth in the claims.